1. Field of the Invention
The present invention relates, in its most general aspect, to the field of the electronics comprising nanometric components and to the nano-manufacturing field.
In particular, the invention relates to a method for realizing a multispacer structure, particularly but not exclusively indicated to be employed as mold in imprint lithography processes in the realization of nanometric circuit architectures.
The invention also relates to a nanometric circuit architecture obtained by means of the above mold.
2. Description of the Related Art
As it is well known, in the field of the electronics, the need of realizing circuit configurations of more and more reduced sizes is particularly felt.
The known technique to meet this need has provided non-photolithographic methods such as, for example, electronic lithography and lithography with X rays, known as lithographic techniques of new generation (NGL—Next generation lithography) and imprint lithography processes.
With these techniques it is possible to realize structures in the nanometric scale (NLS—nanometer length scale), for example to miniaturize crossbar circuit structures up to a density of intersection points of 1011 cm−2, or to obtain highly thickened periodical structures such as arrays having a period lower than 30 nm.
Some examples of these realizations are reported in the publication by N. A. Melosh, A. Boukai, F. Diana, B. Gerardot, A. Badolato, and J. R. Heath, “Ultra High Density Nanowire Lattices and Circuits”, Science 300, 112 (2003) and in the one by M. D. Austin, W. Zhang, H. Ge, D. Wasserman, S. A. Lyon and S. Y. Chou. “6 nm Half-Pitch Lines and 0.04 μM2 Static Random Access Memory Patterns by Nanoimprint Lithography”, Nanotechnology 16, 1058-1061 (2005). A further example is disclosed in the U.S. Pat. No. 6,128,214 by P J. Kuekes et al.
Although advantageous, the lithography with X rays and the electronic one are not exempt from drawbacks such as mainly the need to operate with expensive and complex instruments characterized, moreover, by particularly long etching times.
On the contrary, the imprint lithography processes, which are based on the use of a mold through which a polymer deposited on a substrate is mechanically deformed, are quick and economical.
However, molds with high resolution are generally obtained by using the same electronic lithography with subsequent limitation of the above advantages of the imprint lithography techniques.
Methods are also known based on the Multi-Spacer Patterning Technology (MSPT or SnPT) which are improving with respect to the most advanced lithographic techniques in the realization of repetitive nanometric architectures.
Some examples of these applications are disclosed in the publications “Strategies for Nanoelectronics”, Micr. Eng. 81 (2005) 405-419 (Aug. 8, 2005) and “A Hybrid Approach to Nanoelectronics”, Nanotech. 16 (2005) 1040-1047.
The use of the SnPT for the direct realization of circuit architectures or of structures to be employed as mold in imprint lithography processes is advantageous since this technique has proved to be economical and of simple realization, moreover it allows the attainment of highly critical sizes, in the order of a few nanometers.
However, also the SnPT is not exempt from drawbacks among which the main one is in a non-uniform size of the nanometric spacers obtained, as shown in the electronic micrography of FIG. 1 and in the relative schematic representation of FIG. 2.
In particular, FIG. 2 shows a structure 50 comprising an array of spacers 60 whose height decreases passing from end portions towards the center of the structure itself, i.e., as long as the spacers are obtained at increasing distance from the seed 70.
The above drawback is in reality a serious limitation for these structures, considering that in the electronic nano-manufacturing field the precision and the control of the sizes are very important.